Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional sample-and-hold (S/H) circuit. S/H circuit 100 generally comprises a source 102, a sampling switch S1, and sampling capacitor CS. In operation, source 102 (which has an internal resistance RS) supplies an analog input signal to switch S1. Switch S1 is generally a linear switch having an internal resistance RSH. When switch S1 is actuated, the analog input signal passes to the sampling capacitor CS, so that the capacitor CS can sample the voltage of the analog input signal. When switch S1 is deactuated, capacitor CS holds or stores the voltage of the analog input signal that was sampled.
A problem with this configuration is that capacitor CS is linear, but there is usually an internal nonlinear capacitance CNL. This nonlinear capacitance CNL, when capacitor CS is sampling the analog input signal, causes the capacitor to drawn a nonlinear current. This nonlinear current draw, in turn, causes the final sampled signal to be distorted, predominantly with the third harmonic if the circuit 100 is differential or predominantly with the second harmonic if the circuit 100 is single ended. In particular, this nonlinear current draw is proportional to the rate of change of the terminal voltage, so that the distortion increases with frequency, limiting Spurious-Free Dynamic Range (SFDR) performance in analog-to-digital converter (ADC) applications.
Conventional solutions includes the use of multiple ADCs and differentiators that use the I and Q components of the analog input signal. However, these solutions consume a great deal of power and use a great deal of area. Other conventional circuits are European Patent No. 0910096; U.S. Pat. No. 5,206,543; and U.S. Pat. No. 6,084,440.